Login / Signup

Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU.

Amir CharifAlexandre CoelhoNacer-Eddine ZergainohMichael Nicolaidis
Published in: ASP-DAC (2017)
Keyphrases
  • highly parallelizable
  • network on chip
  • network simulator
  • routing algorithm
  • packet switched
  • special case
  • simulation model
  • bounded treewidth