Formal verification of analog designs using MetiTarski.

William Denman Behzad Akbarpour Sofiène Tahar Mohamed H. Zaki Lawrence C. Paulson

Published in: FMCAD (2009)

Keyphrases

optimal policy
formal verification
model checking
bounded model checking
model checker
automated verification
symbolic model checking
program slicing
analog vlsi
functional verification
temporal logic
formal specification
circuit design
linear temporal logic