A 1.5-GHz sub-sampling fractional-N PLL for spread-spectrum clock generator in 0.18-μm CMOS.

Chun-Yu Lin Tun-Ju Wang Tsung-Hsien Lin

Published in: A-SSCC (2017)

Keyphrases

spread spectrum
high speed
power consumption
image watermarking
low power
data hiding
transform domain
watermarking scheme
video watermarking
watermarking algorithm
direct sequence spread spectrum
bit error rate
digital watermarking
clock frequency
computer simulation
signal processing
cmos technology