Login / Signup
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS.
Ik Joon Chang
Jae-Joon Kim
Sang Phill Park
Kaushik Roy
Published in:
ISSCC (2008)
Keyphrases
</>
random access memory
low voltage
cmos technology
design considerations
flip flops
embedded dram
leakage current
focal plane
power consumption
power line
low power
nm technology
knowledge base
power dissipation
image sensor
file system
main memory