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Asynchronous Multipliers as Combinational Handshake Circuits.
Jaco Haans
Kees van Berkel
Ad M. G. Peeters
Frits D. Schalij
Published in:
Asynchronous Design Methodologies (1993)
Keyphrases
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asynchronous circuits
delay insensitive
logic circuits
high level synthesis
model checking
shift register
tunnel diode
image sequences
vlsi circuits
logic synthesis
parallel architecture
database
high speed
dynamic programming
search algorithm
image processing
genetic algorithm