Abstractions for model checking SDN controllers.
Divjyot SethiSrinivas NarayanaSharad MalikPublished in: FMCAD (2013)
Keyphrases
- model checking
- process algebra
- formal specification
- temporal logic
- partial order reduction
- concurrent systems
- finite state
- control system
- formal methods
- model checker
- automated verification
- temporal properties
- finite state machines
- formal verification
- timed automata
- asynchronous circuits
- reachability analysis
- symbolic model checking
- epistemic logic
- pspace complete
- reinforcement learning
- verification method
- bounded model checking
- computation tree logic
- transition systems
- specification language
- artificial intelligence
- communication protocols
- knowledge based systems