Login / Signup
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.
Cheng-Tao Hsieh
Jason Cong
Zhiru Zhang
Shih-Chieh Chang
Published in:
ASP-DAC (2008)
Keyphrases
</>
power reduction
power dissipation
flip flops
power consumption
low power
hardware implementation
high speed
power saving
multiple input
information flow
hardware architecture
digital signal processing
real time
image processing
multi view
field programmable gate array