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Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration.
Manuel E. Acacio
José González
José M. García
José Duato
Published in:
PDP (2002)
Keyphrases
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shared memory multiprocessors
high speed
low cost
data integration
response time
modular design
prefetching
analog vlsi
high quality
multi view
low latency
programmable logic