A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.
Masafumi OnouchiYusuke KannoMakoto SaenShigenobu KomatsuYoshihiko YasuKoichiro IshibashiPublished in: IEEE J. Solid State Circuits (2010)
Keyphrases
- low power
- power consumption
- high speed
- power reduction
- wide range
- power dissipation
- low cost
- energy dissipation
- wireless transmission
- duty cycle
- high power
- energy efficiency
- power saving
- digital signal processing
- vlsi architecture
- vlsi circuits
- energy saving
- single chip
- low power consumption
- logic circuits
- mixed signal
- clock frequency
- real time
- ultra low power