SMT-centric power-aware thread placement in chip multiprocessors.

Augusto Vega Alper Buyuktosunoglu Pradip Bose

Published in: PACT (2013)

Keyphrases

multithreading
ibm power processor
high speed
parallel computing
chip design
computational power
low cost
power consumption
highly efficient
power dissipation
high density
vlsi implementation
statistical machine translation
parallel implementation
data sets
evolvable hardware
memory subsystem
neural network