Low-Power Lane Detection Unit With Sliding-Based Parallel Segment Detection Accelerator for FPGA.
Heuijee YunDaejin ParkPublished in: IEEE Access (2024)
Keyphrases
- low power
- high speed
- low cost
- low power consumption
- single chip
- lane detection
- power consumption
- gate array
- field programmable gate array
- power reduction
- parallel implementation
- digital signal processing
- driver assistance systems
- hough transform
- lane markings
- detection algorithm
- parallel computing
- logic circuits
- real time
- mixed signal
- detection method
- hardware implementation
- massively parallel
- parallel processing
- cmos technology
- autonomous vehicles
- vehicle detection
- event detection