Timing-Error-Tolerant Network-on-Chip Design Methodology.
Rutuparna TamhankarSrinivasan MuraliStergios StergiouAntonio PulliniFederico AngioliniLuca BeniniGiovanni De MicheliPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2007)
Keyphrases
- design methodology
- error tolerant
- network on chip
- power dissipation
- routing algorithm
- network simulator
- graph matching
- multi processor
- data transfer
- design process
- fuzzy neural network
- object oriented
- formal specification
- subgraph isomorphism
- association patterns
- pattern recognition
- object recognition
- wireless sensor networks
- database systems
- shared memory
- neural network
- power consumption
- business intelligence
- shortest path
- building blocks
- low cost