A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs.

Jongsun Kim S. W. Han

Published in: IEICE Electron. Express (2018)

Keyphrases

low power
duty cycle
mixed signal
power consumption
high speed
low cost
vlsi circuits
single chip
real time
cmos technology
low power consumption
digital signal processing
logic circuits
vlsi architecture
multi channel
cmos image sensor
power dissipation
power reduction
image sensor
gate array