SAT-based equivalence checking of threshold logic designs for nanotechnologies.
Yexin ZhengMichael S. HsiaoChao HuangPublished in: ACM Great Lakes Symposium on VLSI (2008)
Keyphrases
- bounded model checking
- answer set programming
- logic programming
- linear temporal logic
- classical logic
- formal verification
- strong equivalence
- ai planning
- active learning
- verification method
- version space
- application specific integrated circuits
- logical framework
- multi valued
- sat solvers
- modal logic
- digital circuits
- predicate logic
- automated reasoning
- knowledge representation
- reinforcement learning