Login / Signup

Study on the single-event upset sensitivity of 65-nm CMOS sequential logic circuit.

Sai LiJianwei HanRui ChenShipeng ShangguanYingqi MaXuan Wang
Published in: IEICE Electron. Express (2020)
Keyphrases
  • high speed
  • circuit design
  • delay insensitive
  • digital circuits
  • low cost
  • neural network
  • empirical studies
  • logic programming
  • infrared
  • power consumption
  • event detection
  • low power
  • multi valued
  • analog vlsi