Modeling Logic Gates and Circuits with Generalized Nets.

Lenko Erbakanov Todor Kostadinov Todor Petkov Sotir Sotirov Veselina Bureva

Published in: IWIFSGN@FQAS (2015)

Keyphrases

logic circuits
delay insensitive
logic synthesis
digital circuits
asynchronous circuits
databases
machine learning
genetic algorithm
learning algorithm
high speed
chip design