Clock-gated and low-power standard cell library for ISFET Two-Point Calibration processor chip.
Wen-Yaw ChungJian-Ping ChangFebus Reidj G. CruzPublished in: APCCAS (2010)
Keyphrases
- low power
- high speed
- single chip
- power consumption
- low cost
- mixed signal
- gate array
- low power consumption
- cmos technology
- real time
- high power
- wireless transmission
- ultra low power
- digital signal processing
- image sensor
- logic circuits
- clock frequency
- vlsi circuits
- signal processor
- focal plane
- power saving
- vlsi architecture
- power management
- power dissipation
- power reduction
- cmos image sensor
- nm technology
- high density
- energy efficiency