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Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations.

Michitarou YabuuchiKazutoshi Kobayashi
Published in: IPSJ Trans. Syst. LSI Des. Methodol. (2016)
Keyphrases
  • logic circuits
  • real time
  • low power
  • pattern recognition
  • hidden markov models
  • high speed
  • multistage
  • network traffic
  • data flow