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A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.
Hangi Park
Chanwoong Hwang
Taeho Seong
Jaehyouk Choi
Published in:
IEEE J. Solid State Circuits (2022)
Keyphrases
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digital holography
range data
objective function
wide range
high levels
three dimensional
training phase
digital media
maximum margin
preprocessing phase
real time
particle swarm optimization
learning phase
reduction method