Login / Signup

472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device.

Jeong-Gun LeeDeok-Young LeeMyeong-Hoon OhYoung Woong Ko
Published in: IEICE Electron. Express (2011)
Keyphrases
  • image segmentation
  • fpga device
  • hardware implementation
  • field programmable gate array
  • response time
  • neural network
  • high level
  • high speed
  • steady state
  • hardware design
  • hardware architecture
  • fpga technology