A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI.
Robert PawlowskiEvgeni KrimerJoseph CropJacob PostmanNariman Moezzi MadaniMattan ErezPatrick ChiangPublished in: ISSCC (2012)
Keyphrases
- silicon on insulator
- parallel processing
- single instruction multiple data
- ibm power processor
- parallel architectures
- highly parallel
- dynamic random access memory
- massively parallel
- parallel processors
- parallel algorithm
- high speed
- traffic flow
- single chip
- instruction set
- floating point unit
- error resilience
- processing elements
- multiprocessor systems
- mesh connected
- motion vectors
- detection algorithm