A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps.
Ting-Jung LinWei ZhangNiraj K. JhaPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2014)
Keyphrases
- efficient implementation
- hardware implementation
- fine grain
- reconfigurable architecture
- systolic array
- coarse grain
- parallel architecture
- field programmable gate array
- xilinx virtex
- reconfigurable hardware
- hardware architecture
- parallel computation
- hardware design
- distributed memory
- data flow
- single chip
- nested transactions
- image processing algorithms
- signal processing
- real time
- parallel computing
- low cost
- general purpose
- mobile devices