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An 82-107.6-GHz Integer-N ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta-Sigma TDC.
Zhiqiang Huang
Howard C. Luong
Published in:
IEEE J. Solid State Circuits (2019)
Keyphrases
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delta sigma
high speed
user friendly
power consumption
noise shaping
phase locked loop
high voltage
fault diagnosis
shortest path
analog to digital converter
low power
power system
multiscale
low cost
input image
image processing
transmission line
clock frequency