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Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process.
Ming-Dou Ker
Wen-Yi Chen
Kuo-Chun Hsu
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2006)
Keyphrases
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cmos technology
low voltage
power dissipation
high speed
power consumption
user interface
low power
design considerations
power reduction
design process
input output
silicon on insulator
ibm power processor
power line
power management
design methodology
image processing
circuit design
embedded systems
parallel processing
signal processing
mobile devices
real time