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Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing.

Mutsuo DaitoYoshiro NakataSatoshi SasakiHiroyuki GomyoHideki KusamitsuYoshio KomotoKunihiko IizukaKatsuyuki IkeuchiGil-Su KimMakoto TakamiyaTakayasu Sakurai
Published in: IEEE J. Solid State Circuits (2011)
Keyphrases
  • high speed
  • real time
  • low level
  • higher level
  • integrated circuit
  • data structure
  • low cost
  • software testing