Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder.
Si-Yun J. LiTyler L. BrandonDuncan G. ElliottVincent C. GaudetPublished in: SiPS (2012)
Keyphrases
- ldpc codes
- low density parity check
- fpga implementation
- distributed source coding
- distributed video coding
- high speed
- turbo codes
- decoding algorithm
- power consumption
- hardware implementation
- low cost
- error correction
- message passing
- low complexity
- rate allocation
- signal processing
- low power
- error concealment
- channel coding
- hardware architecture
- computer simulation