A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology.
Kezhen ZhuShunyu LiGuangyong ChuPublished in: IEICE Electron. Express (2023)
Keyphrases
- multistage
- cmos technology
- low power
- decision feedback
- high speed
- power consumption
- spl times
- parallel processing
- low voltage
- single stage
- dynamic programming
- lot sizing
- silicon on insulator
- image sensor
- power dissipation
- multipath
- low cost
- error propagation
- optimal policy
- machine learning
- digital camera
- image sequences
- ad hoc networks
- real time