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In-system failure investigation on 0.18 μm high speed serial link ASIC using logic built-in self test.
Jeanne Trinko Mechler
Raymond J. Bulaga
Jon Garlett
Published in:
CICC (2003)
Keyphrases
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built in self test
integrated circuit
high speed
low power
real time
link failure
single chip
high speed networks
failure prediction
data sets
modal logic
application specific
link structure
failure detection