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One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.
Wang Kang
Weisheng Zhao
Lun Yang
Jacques-Olivier Klein
Youguang Zhang
Dafine Ravelosona
Published in:
NVMSA (2014)
Keyphrases
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high speed
error correction
error correcting
error control
design considerations
random access memory
post processing
low power
classical logic
multi valued
real time
modal logic
logical operations
logic programming
asynchronous circuits
power consumption
content addressable