A 1.2 - 6.4 GHz clock generator with a low-power DCO and programmable multiplier in 40-nm CMOS.
Tero TikkaKari StadiusJussi RyynänenMartti VoutilainenPublished in: ISCAS (2014)
Keyphrases
- low power
- power consumption
- clock gating
- cmos technology
- single chip
- high speed
- clock frequency
- signal processor
- low cost
- nm technology
- power reduction
- low voltage
- power management
- cmos image sensor
- general purpose
- high power
- power dissipation
- vlsi circuits
- digital signal processing
- hardware implementation
- mixed signal
- silicon on insulator
- low power consumption
- image sensor
- wireless transmission
- vlsi architecture
- power saving
- floating point
- delay insensitive
- frame rate
- gate array
- low complexity