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A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS.
Sai Zhang
Jane S. Tu
Naresh R. Shanbhag
Philip T. Krein
Published in:
IEEE J. Solid State Circuits (2014)
Keyphrases
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cmos technology
nm technology
low voltage
low power
power consumption
low cost
management system
computational intelligence
design considerations
software and hardware implementations
high speed