A cryogenic low power CMOS analog buffer at 4.2K.
Yajie HuangChao LuoTengteng LuYuanke ZhangJun XuGuoping GuoPublished in: IEICE Electron. Express (2021)
Keyphrases
- low power
- mixed signal
- vlsi architecture
- power consumption
- vlsi circuits
- high speed
- low cost
- cmos image sensor
- single chip
- cmos technology
- image sensor
- wide dynamic range
- analog to digital converter
- low power consumption
- wireless transmission
- high power
- digital signal processing
- analog vlsi
- gate array
- multi channel
- power reduction
- low voltage
- logic circuits
- focal plane
- power dissipation
- digital circuits