Enhanced low power motion estimation VLSI architectures for video compression.
Mohamed A. ElgamelAhmed M. ShamsXi XuelingMagdy A. BayoumiPublished in: ISCAS (4) (2001)
Keyphrases
- video compression
- low power
- motion estimation
- high speed
- single chip
- vlsi circuits
- motion compensation
- gate array
- vlsi architecture
- power consumption
- low cost
- video coding
- motion compensated
- power dissipation
- low complexity
- video conferencing
- mixed signal
- block matching
- motion vectors
- low bit rate
- bit allocation
- inter frame
- motion model
- image sequences
- video sequences
- logic circuits
- reference frame
- video data
- low power consumption
- motion field
- super resolution
- computer vision
- optical flow
- compression ratio
- block matching algorithm
- rate distortion
- spatial domain
- motion estimator
- distributed video coding
- temporal redundancy
- macroblock
- cmos technology
- vlsi implementation
- real time
- signal processing
- real time video processing