Preliminary Results from a 49-Channel Neural Recording ASIC with Embedded Spike Compression in 28 nm CMOS.
William LemaireEsmaeil Ranjbar KoleibiTakwa OmraniMaher BenhouriaKonin KouaCharles QuesnelLouis-Philippe GauthierJérémy MénardKeven GagnonSébastien RoyRéjean FontainePublished in: NEWCAS (2022)
Keyphrases
- circuit design
- spike trains
- embedded dram
- dynamic random access memory
- random access memory
- single chip
- spiking neurons
- cmos technology
- embedded image
- silicon on insulator
- network architecture
- metal oxide semiconductor
- integrated circuit
- neural network
- channel coding
- image compression
- compression scheme
- low power
- compression algorithm
- hodgkin huxley
- high speed
- embedded systems
- low cost
- neuronal networks
- compression ratio
- power consumption
- nm technology
- data compression
- hardware implementation
- design methodology
- neural fuzzy
- hardware architecture
- multi channel
- hebbian learning
- physical design
- neural model
- application specific