A 27% active and 85% standby power reduction in dual-power-supply SRAM using BL power calculator and digitally controllable retention circuit.
Fumihiko TachibanaOsamu HirabayashiYasuhisa TakeyamaMiyako ShizunoAtsushi KawasumiKeiichi KushidaAzuma SuzukiYusuke NikiShinichi SasakiTomoaki YabeYasuo UnekawaPublished in: ISSCC (2013)
Keyphrases
- power reduction
- power supply
- power consumption
- power dissipation
- low power
- high power
- power saving
- energy supply
- single phase
- intelligent control
- energy saving
- data center
- high frequency
- energy efficiency
- electrical power
- multithreading
- high speed
- dc dc converter
- clock gating
- low cost
- solar energy
- rbf neural network
- cmos technology