UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI.
Kyu-won ChoiAbhijit ChatterjeePublished in: ISLPED (2003)
Keyphrases
- ultra low power
- low power
- high speed
- power consumption
- cmos technology
- power dissipation
- single chip
- vlsi circuits
- low cost
- chip design
- mixed signal
- optimization algorithm
- global optimization
- optimization problems
- combinatorial optimization
- optimization method
- image sensor
- evolutionary algorithm
- power losses
- vlsi design
- real time
- focal plane
- optimization model
- optimization process
- signal processing
- neural network
- data sets