Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs.

Suleyman Tosun Hakduran Koc Nazanin Mansouri

Published in: VLSI (2003)

Keyphrases

model checking
data flow
face verification
formal verification
real time
verification method
neural network
real world
social networks
feature selection
temporal logic
design tools
linear array