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Effects of asymmetric underlap spacers on nanoscale junctionless transistors and design of optimised CMOS amplifiers.
Debapriya Roy
Abhijit Biswas
Published in:
IET Circuits Devices Syst. (2019)
Keyphrases
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circuit design
power consumption
low power
design space
cmos technology
case study
design process
design principles
design decisions
design methodology
database
social networks
building blocks
engineering design
single chip