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Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS.

Amaury NèveDenis FlandreHelmut SchettlerThomas LudwigGerhard Hellner
Published in: ISLPED (2002)
Keyphrases
  • circuit design
  • real time
  • high speed
  • single chip
  • database
  • artificial intelligence
  • building blocks
  • pattern matching
  • design principles
  • design decisions
  • design methodology
  • power dissipation