Design guideline for resistive termination of on-chip high-speed interconnects.

Akira Tsuchiya Masanori Hashimoto Hidetoshi Onodera

Published in: CICC (2005)

Keyphrases

high speed
low power
single chip
case study
power dissipation
power consumption
cmos technology
neural network
circuit design
computer aided
input output
low cost
design principles
physical design
user interface
real time
vlsi implementation
vlsi design
user centred
chip design