Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate.
Nabihah AhmadS. M. Rezaul HasanPublished in: Integr. (2013)
Keyphrases
- s box
- cmos technology
- low power
- nm technology
- power consumption
- block cipher
- low cost
- high speed
- single chip
- advanced encryption standard
- low voltage
- power dissipation
- initial conditions
- mixed signal
- low power consumption
- digital signal processing
- vlsi circuits
- vlsi architecture
- ultra low power
- logic circuits
- efficient implementation
- silicon on insulator
- power reduction
- gate array
- encryption algorithm
- parallel processing
- hash functions
- image sensor
- ciphertext
- lightweight