Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking.
Tomoya KitaniYoshifumi TakamotoIsao NakaKeiichi YasumotoAkio NakataTeruo HigashinoPublished in: FPL (2003)
Keyphrases
- model checking
- formal verification
- temporal logic
- finite state
- hardware architecture
- transition systems
- symbolic model checking
- temporal properties
- hardware implementation
- automated verification
- verification method
- reachability analysis
- pspace complete
- model checker
- formal specification
- knowledge based systems
- bounded model checking
- computation tree logic
- xilinx virtex
- knowledge base
- linear temporal logic
- timed automata
- formal methods
- finite state machines
- object oriented