Reconfigurable memory based AES co-processor.
Ricardo ChavesGeorgi KuzmanovStamatis VassiliadisLeonel SousaPublished in: IPDPS (2006)
Keyphrases
- digital signal
- systolic array
- reconfigurable architecture
- functional units
- low cost
- computation intensive
- parallel architecture
- hardware implementation
- parallel processing
- computer architecture
- single chip
- memory based learning
- neural network
- functional verification
- general purpose
- parallel architectures
- secret key
- high speed