A 0.1~4GHz receiver and 0.1~6GHz transmitter with reconfigurable 10~100MHz signal bandwidth in 65nm CMOS.
Xinwang ZhangYun YinMeng CaoZhigang SunLing FuZhaokang XiaHongxing FengXing ZhangBaoyong ChiMing XuZhihua WangPublished in: CICC (2012)
Keyphrases
- high speed
- clock frequency
- cmos technology
- received signal
- power consumption
- low power
- low cost
- high frequency
- signal to noise ratio
- power supply
- power reduction
- signal processing
- dielectric constant
- frequency band
- nm technology
- noise ratio
- frequency domain
- digital signal
- wireless communication systems
- low voltage
- amplitude modulation