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Time-Triggered Switch-Memory-Switch Architecture for Time-Sensitive Networking Switches.
Zonghui Li
Hai Wan
Yangdong Deng
Xibin Zhao
Yue Gao
Xiaoyu Song
Ming Gu
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
Keyphrases
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gigabit ethernet
high speed
real time
packet switching
memory usage
management system
main memory
memory requirements
software architecture
associative memory
distributed computing
network architecture
limited memory
switched networks
functional verification