An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimization.
Henry BlockTsutomu MaruyamaPublished in: FPL (2017)
Keyphrases
- hardware implementation
- phylogenetic trees
- field programmable gate array
- fpga implementation
- signal processing
- efficient implementation
- hardware architecture
- computational biology
- software implementation
- hardware design
- dedicated hardware
- image processing algorithms
- tree structures
- evolutionary history
- fpga device
- optimization problems
- fpga technology
- parallel architecture
- pipelined architecture
- natural language
- tree structure
- maximum likelihood
- low cost
- probability distribution
- feature extraction
- maximum parsimony