Isodelay output driver design using step-wise charging for low power.
Atul KatochHarry J. M. VeendrickPublished in: ESSCIRC (2005)
Keyphrases
- low power
- step wise
- single chip
- power consumption
- high speed
- low cost
- low power consumption
- vlsi architecture
- logic circuits
- gate array
- mixed signal
- high power
- power dissipation
- digital signal processing
- vlsi circuits
- design process
- power reduction
- cmos technology
- real time
- design considerations
- design methodology
- embedded systems
- motion estimation