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A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES Architecture.
Tian Xiang
Lei Zhao
Xi Jin
Tianqi Wang
Shaoping Chu
Cong Ma
Shubin Liu
Qi An
Xue Ben
Published in:
FCCM (2014)
Keyphrases
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management system
real time
sigma delta
network architecture
software architecture
data mining
preprocessing phase
social networks
distributed architecture
duty cycle
mixed signal
high speed
case study
artificial intelligence
neural network
databases
data sets