Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming.
Ranga VemuriR. KalyanaramanPublished in: IEEE Trans. Very Large Scale Integr. Syst. (1995)
Keyphrases
- constraint programming
- constraint satisfaction problems
- constraint propagation
- constraint satisfaction
- combinatorial problems
- np hard problems
- finite domain
- circuit design
- model based diagnosis
- highly efficient
- hardware design
- global constraints
- data mining
- search strategies
- model checking
- dynamic programming
- lower bound