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Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.
Woo-Rham Bae
Gyu-Seob Jeong
Yoonsoo Kim
Hankyu Chi
Deog-Kyoon Jeong
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2016)
Keyphrases
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cmos technology
power dissipation
low power
power consumption
spl times
low voltage
high speed
parallel processing
mixed signal
silicon on insulator
single chip
low cost
user interface
design process
design methodology
digital signal processing
digital images
pattern recognition
video sequences
computer vision